Nowadays, the System on Chip (SoC) industry is rapidly developing. One of the objectives of SoC developers is to provide the most efficient communication between computational units. One of the possible solutions is using Networks on Chip (NoC) of various topologies with different routing algorithms. In this paper, a configurable test environment designed for cycle-accurate NoC simulation as part of a SoC, used to provide statistics about network behavior during test process, is presented. The environment is designed to evaluate NoC performance as part of a specific SoC at the development stage, when there is a full or partial RTL description of the system. The environment configuration options, its application area, general scheme and calculated NoC performance characteristics are considered. As a conclusion, an example of using the environment to evaluate the performance of a specific NoC is described in detail.

Keywords: network on chip, system on chip, performance evaluation, verification