The aim of this work was the use of practical testing of a software module of topology synthesis of a IC design flow, built on the basis of EDA modules one of the leading companies, Cadence Design Systems. System compatibility with Cadence modules is achieved by using of input and output files in standard formats of data exchange - LEF and DEF. Because the data files are text format, it allows customization in any configuration of the IC and library basis. The developed software system can be used both on routing stage and use to synthesis topology (solving the placement and routing problems). Developed design flow have been tested on three projects based chipset analog-to-digital FPGA (CMOS technology on bulk silicon with 2.6 micron design rules). The developed software system can be used as a step trace compounds and to comply fully with the synthesis of topology, solving the problem of locating elements of the project and laying tracks.Positive practical results obtained allow us to conclude about the correctness of the developed algorithms, and the overall system performance.
Keywords: topology synthesis, IC, design flow, routing, placement and routing problems